Tuning thermal transport in Si nanowires by isotope engineering.

Preparation and Characterization of Tin Oxide Nanowires

The aim of this research is preparation of SnO2 nanowires by means of Thermal chemical reaction vapor transport deposition (TCRVTD) method from SnO powders. The morphology, chemical composition and microstructure properties of the nanowires are characterized using field emission scanning electron microscope (FE-SEM), EDS, and XRD. The XRD diffraction patterns reveal that the SnO2 nanowires have...

Ultralow thermal conductivity of isotope-doped silicon nanowires.

The thermal conductivity of silicon nanowires (SiNWs) is investigated by molecular dynamics (MD) simulation. It is found that the thermal conductivity of SiNWs can be reduced exponentially by isotopic defects at room temperature. The thermal conductivity reaches the minimum, which is about 27% of that of pure 28Si NW, when doped with 50% isotope atoms. The thermal conductivity of isotopic-super...

Tuning Lattice Thermal Conductance by Porosity Control in Ultrascaled Si and Ge Nanowires

Transport modulation in Ge/Si core/shell nanowires through controlled synthesis of doped Si shells.

Appropriately controlling the properties of the Si shell in Ge/Si core/shell nanowires permits not only passivation of the Ge surface states, but also introduces new interface phenomena, thereby enabling novel nanoelectronics concepts. Here, we report a rational synthesis of Ge/Si core/shell nanowires with doped Si shells. We demonstrate that the morphology and thickness of Si shells can be con...

Gate-All-Around Silicon Nanowire MOSFETs: Top-down Fabrication and Transport Enhancement Techniques

Scaling MOSFETs beyond 15 nm gate lengths is extremely challenging using a planar device architecture due to the stringent criteria required for the transistor switching. The top-down fabricated, gate-all-around architecture with a Si nanowire channel is a promising candidate for future technology generations. The gate-all-around geometry enhances the electrostatic control and hence gate length...